The electronic microcircuit, or "chip," in which a large number of electrical circuit components are diffused, for example, onto the surface of a 1 to 4 cm.sup.2 chip of silicon or germanium, has become an integral and indispensable part of our industrial technology. The industrial significance of this technology is so great that continuous efforts are being made to improve chip performance, reliability and service life.
The delicate structure and very small size of these chips, however, have created unusually novel and difficult technical problems. These problems, generally caused by physical phenomena that are well known on a macroscopic scale, e.g., coefficients of thermal expansion (CTE), heat dissipation, adhesive shrinkage, flexural moduli, and the like nevertheless create entirely new and often undesirable sets of effects when they manifest themselves in the microscopic domain of the electronic chip.
Illustratively, a typical chip is mounted on and is electrically coupled to a supporting substrate. The substrate, in turn, is secured to a printed circuit board. Thus, the substrate not only serves the intermediate function of coupling electrical signals taken from conductors on the printed circuit board to the chip for processing, but also takes output signals from the chip and applies these output signals to other printed circuit board conductors for further processing.
Because a chip, when energized, generates a considerable amount of heat, which can be on the order of 50 to 100 watts emanating from a chip with an area of 1 to 4 cm.sup.2, the CTE for the chip and that of its substrate can produce a number of very damaging effects. Controlling this heat, generated in so concentrated an area, in a manner that avoids chip failure through overheating is a problem that has not yet been solved in a fully satisfactory way.
For instance, one source of thermally related chip failure resides in the fact that the electrical characteristics of the circuit components that are diffused or otherwise impressed on the chip can vary markedly with changes in chip dimensions. These chip dimension changes, caused, for example, by thermal expansion of the chip, can make the expanded chip produce useless and, perhaps, damage output signals. These undesired thermal expansion effects can also cause the central portion of a chip, secured at its margins to a substrate, to curve, bend or bow. This curving frequently causes at least some of the electrical connections between the chip and its underlying substrate to separate and disconnect from each other. Largely for these reasons, chip performance is degraded.
Unquestionably, this destruction of circuit continuity through a thermal expansion induced electrical connection failure is a CTE consequence that must be at least minimized if it can not be fully avoided.
Other destructive effects that are attributable to thermally induced curving include chip cracking and breaking. In this circumstance, chips crack and break in large measure because tensile stresses are established in the outermost surface of the chips as the chips are bent. These stresses, should they exceed the fracture strength of the chip, will cause the chip to crack or break. Thermal effects are not limited to the chip, but also appear in the substrate and in other chip packaging materials.
A substrate is a structure that is assembled by stacking together two to fifteen or more layers of substrate materials, at least two of these layers being of different compositions. The materials from which each of these layers are formed tend to be quite diverse, some layers, for instance, being metal (e.g., copper, nickel or gold), other illustrative layers being an epoxy resin and glass compound. The CTE for these individual layers, each being considerably different, invite an uncontrolled bending or thermally induced substrate surface distortion that is applied not only to the chip during circuit operation, but also to the substrate through the high temperatures that are required in substrate manufacture.
Preferably, the substrate surfaces that support the chip and establish electrical contact between the chip and the printed circuit board should be "flat" in all conditions of operation. Indeed, if the substrate itself is not sufficiently "flat", it will prove impossible to establish electrical contact between the chip and substrate.
There are, moreover, other ways in which the desired degree of substrate flatness can be destroyed, apart from CTE-related effects. One of these non-CTE related losses in flatness is found in the inability to control completely individual layer thickness in the layer manufacturing process. These individual layer thickness variations depart from standard or preferred thicknesses not only among different production lots, but also in different portions or areas of the same layer. These variations in individual layer thickness can contribute to localized variations in the coefficient of thermal expansion (CTE) within a substrate, which may contribute to warping of the substrate.
To establish some standard for judging flatness in these microscopic circumstances, and thus to distinguish acceptable variations in flatness from those that are industrially not acceptable, several criteria have been established. First, "flatness" for the purpose of chip mounting and packaging has been defined as the ratio of the maximum high to low deviation per unit area and has developed into an industry practice in which the maximum acceptable deviation from flatness is 2.5 .mu.m. Further, there are other industrially accepted standards for warpage, or loss in flatness for an entire chip package and the chip package components, in which warpage of more than 6 to 8 mils over the entire chip package is industrially unacceptable. This is a goal that is difficult to achieve, but it is a goal nevertheless, that the chip packaging industry must meet, in spite of the fact that thickness deviations in a given substrate layer can be as much as 15%.
In an attempt to solve or at least to cope with these curvature or bending problems, the chip packaging industry has moved in two entirely opposite directions. Ceramic substrates of about 40 mils or greater in thickness have been used. These thick substrates are so massive, relative to the supported chip, that chip bending does not occur.
The other, opposite, industrial approach has been to use substrates that are essentially thin films, e.g., about 2 mils or less in thickness. These thin substrate films deform and absorb almost all of the compressive stresses, surface irregularities and the like, thus leaving the chip in an essentially flat, undeformed condition, similar to the way in which "blister" or "shrink-wrap" packaging conforms itself to the shape of the packaged item.
In passing, it also should be noted that there are sources of chip warpage other than those described above. One illustrative non-thermally or production related source of warpage is a consequence of the adhesive underfill that is applied between opposing surfaces of the chip and the corresponding substrate area to secure the chip to the substrate and to stabilize the electrical connections between the chip and its substrate. The electrical connections in this substrate area directly under the chip, often referred to as the die area, usually are soldered joints. In this respect, the solder on these joints, over time, is subject to a deterioration that weakens and destroys the electrical connections within the die area. This deterioration in the soldered joints has a number of sources, one of these sources being a fatigue that is induced through relative movement between the chip and its substrate. Although filling the volume within the die area between the soldered joints with an adhesive (usually an epoxy resin cement) bonds the chip to the substrate and reduces relative movement as a source of the soldered joint deterioration, the adhesive does produce some undesirable side effects. For instance, on curing or hardening, the adhesive becomes a further locus of undesirable structural stress. The cured adhesive shrinks, placing the soldered joints in compression and through these compressive forces thereby applies still another curving movement to the chip and the substrate.
Clearly, these techniques for coping, with greater or lesser success, with curving or bending moments, whatever their source, in massive substrates of about 40 mils or more in thickness or in thin film substrates of about 2 mils or less nevertheless fail to suggest any solution for corresponding problems among intermediate range substrates with thicknesses greater than 2 mils and thinner than 40 mils.
Substrates in this intermediate range are too thin to force the chip to maintain a suitable degree of flatness. These intermediate range substrates are also too thick to absorb all of the bending moments, whatever the source, to enable the relatively thicker chip to structurally dominate the combination and maintain an all-important chip flatness. It has been found, in fact, that substrates in this intermediate range are excellent vehicles for transmitting bending stresses to their respective chips, thereby aggravating the chip bending stress difficulties summarized above. Nevertheless, in spite of these structural limitations, there is a significant commercial demand for chip substrates in this intermediate thickness range.
To complete a chip package, the chip usually is mounted in the center of the substrate. A ring to stiffen the chip and substrate combination often is bonded or secured to the substrate by means of an adhesive that is applied to the margin of the substrate, essentially enclosing the chip within the ring's center either before or after mounting the chip. The ring forms a frame around the chip with the inner perimeter of the ring being spaced from the corresponding edges of the chip and the height of the ring being somewhat greater than that of the chip. In this way, a lid, or cover, joined to that surface of the ring opposite to the ring surface that is bonded to the substrate, is spaced above the corresponding die area of the chip, leaving a gap between the upper surface of the chip and the opposing, die area surface of the lid that later is filled with a thermally conducting material.
The CTE, adhesive shrinkage, flatness irregularities and other sources of warping, bending and distortion considered above apply with essentially equal force to the ring and to the lid. Accordingly, to produce a marketable chip package these undesirable stress and bending effects, particularly for chips that have substrates with thicknesses greater than 2 mils and thinner than 40 mils, and more particularly between 5 mils and 25 mils, should be avoided, or at least controlled and reduced in order to maintain chip and chip component flatness within the acceptable degree of flatness that is defined in relevant industrial practice and standards.